In integrated circuit formation technologies, thermal budget, dopant concentration and dopant depth of source and drain regions are continuously reduced for short channel effect improvement. However, such reductions result in lower polysilicon gate dopant concentrations in metal-oxide-semiconductor (MOS) devices. When the dopant concentration in a polysilicon gate is lower than a threshold value, a depletion layer is induced at the interface between the polysilicon gate and the underlying gate dielectric, resulting in an increased effective dielectric thickness and a degraded saturation current.
In order to solve this problem, a pre-gate doping process was commonly used for improving the performance of MOS devices. In a typical pre-gate doping process, after the formation, but before the patterning, of a gate dielectric layer and a polysilicon layer, the polysilicon layer was implanted with desired dopants. An annealing was then performed to drive the dopants down and also to activate the dopants. This process increased the dopant concentration at the interface between polysilicon gates and the respective underlying gate dielectrics, and thus eliminated the depletion layers.
The conventional pre-doping process, however, suffers limitations. FIG. 1 illustrates a cross-sectional view of an intermediate stage in a conventional pre-doping process. P-well region 2 and n-well region 4 are separated from each other by shallow trench isolation (STI) region 6. Gate dielectric layer 8 is formed on p-well region 2, n-well region 4 and STI 6, followed by the formation of polysilicon layer 10. Mask 12 is formed to cover p-well region 2, and p-type dopants are implanted into polysilicon region 102, which is over n-well region 4. Mask 12 is then removed, and mask 14 as shown in dotted lines, is formed. N-type dopants are implanted into polysilicon region 101, which is over p-well region 2. An annealing is then performed to drive the implanted dopants, which are typically in an upper portion of polysilicon layer 10, down into the lower portion of polysilicon layer 10, as is symbolized by arrows 16.
Adversely, at the time the dopants are driven downward, an inter-diffusion, which is symbolized by arrow 18, also occurs. This causes the lateral diffusion of p-type dopants into polysilicon region 101, and the lateral diffusion of n-type dopants into polysilicon region 102. After the patterning of polysilicon layer 10 and dielectric layer 8, the gate poly of a resulting NMOS device will adversely contain p-type dopants, and the gate poly of a resulting PMOS device will adversely contain n-type dopants. The adversely diffused dopants neutralize portions of the desired dopants, causing the fluctuation in threshold voltages.
The above-discussed problem becomes worse in small-scale integrated circuits. For example, in integrated circuits formed using 65 nm technology, the clearance distance D between implanted p-type dopants and the gate poly of the neighboring NMOS device is only about 70 nm, while thickness T of polysilicon layer 10 is about 100 nm, which is even greater than the clearance distance D. The lateral diffusion is severe and cannot be ignored. The problem will increase in severity if lower-scale technologies are used. Therefore, this problem limits the improvement in future device performance and device optimization.
Accordingly, what is needed in the art are semiconductor structures and formation methods that incorporate pre-doping thereof to take advantage of the benefits associated with the increased dopant concentration while at the same time overcoming the deficiencies of the prior art.